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ADC-321
OBSOLETE PRODUCT
FEATURES
Low power dissipation (180mW max.) Input signal bandwith (100MHz) Optional synchronized clamp function Low input capacitance (15pF typ.) +5V or +5V /+3.3V power supply operation Differential nonlinearity (1/2LSB max.) Optional self-biased reference CMOS/TTL compatible inputs Outputs 3-state TTL compatible Surface mount package
INPUT/OUTPUT CONNECTIONS Pin Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BIT 8 (LSB) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (MSB) TEST +DVS (Digital) TEST A/D CLOCK NO CONNECTION NO CONNECTION CLAMP IN (CLP) +AVS (Analog)
8-Bit, 50MHz 8-Bit, 50MH Video A/D Converter 0
Contact Factory for Replacement Model
Pin 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Function NO CONNECTION DIGITAL GROUND (DGND) OUTPUT ENABLE (OE) CLAMP ENABLE (CLE) DIGITAL GROUND (DGND) CLAMP CONTROL (COP) CLAMP REF. (VREF) REF. BOTTOM SENSE (VRBS) REF. BOTTOM (VRB) ANALOG GROUND (AGND) ANALOG GROUND (AGND) ANALOG IN (VIN) +AVS (Analog) +AVS (Analog) REF. TOP (VRT) REF. TOP SENSE (VRTS)
PRODUCT OVERVIEW
The ADC-321 is an 8-bit, high speed, monolithic CMOS, sub-ranging A/D converter. The ADC-321 achieves a sampling rate comparable to flash converters by employing a sub-ran single +5V or dual +5V and +3.3V power source to allow easy interfacing with 3.3V logic. An optional synchronous clamp function useful for video signal processing is provided. The ADC-321 is well suited for the portable video signal processors due to its low 125mW typical power dissipation. The ADC-321 also features 0.5 LSB max. differential non-linearity, a self bias function that can eliminate the need for external references, SNR with THD of 45dB, a small 32-pin QFP package and an operating temperature range of -40 to +85C
+AVS 16 VRTS 17 VRT 18 +AVS 19 Reference Supply
30 OUTPUT ENABLE 31 DGND A 4-Bit Lower Sampling Comparator B A 1 4-Bit Lower Encoder B Lower Data Latch 2 3 4 BIT 8 (LSB) BIT 7 BIT 6 BIT 5
+AVS 20
VIN 21
AGND 22 5 AGND 23 VRB 24 VRBS 25 12 A/D CLOCK Clock Generator 4-Bit Upper Sampling Comparator 4-Bit Upper Encoder Upper Data Latch 6 7 8 BIT 4 BIT 3 BIT 2 BIT 1 (MSB)
- VREF 26 DGND 28 CLAMP CONTROL 27 CLAMP ENABLE 29 For full details go to www.murata-ps.com/rohs + D-FF 15 CLAMP IN 9 TEST (Open)
10 +DVS 11 TEST (Open)
Figure 1. ADC-321 Functional www.murata-ps.com Block Diagram Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000 MDA_ADC-321.B01 Page 1 of 8
ADC-321
8-Bit, 50MHz Video A/D Converter
ABSOLUTE MAXIMUM RATINGS (TA = +25C)
PARAMETERS Power Supply Voltage (+AVS, +DVS) Analog Input Voltage, (VIN) Reference Input Voltage (VRT, VRB) Digital Input Voltage (VIH, VIL) Digital Output Voltage (VOH, VOL) LIMITS -0.5 to 7 -0.5 to +AVS + 0.5 -0.5 to +AVS + 0.5 -0.5 to +AVS + 0.5 -0.5 to +DVS + 0.5 UNITS Volts Volts Volts Volts Volts DIGITAL OUTPUTS Output Data Delay (OE = 0V, CL = 15pF) (@ +DVS = +5V)
(continued)
MIN.
TYP.
MAX.
UNITS
FUNCTIONAL SPECIFICATIONS
Typical at TA = 25C, VRT = +2.5V, VRB = +0.5V, +AVS = +5V, +DVS = +3V to +5.5V, FS = 50MHz unless otherwise specified. ANALOG INPUTS Input Voltage Range Input Capacitance (@ VIN = +1.5Vdc +0.07VRMS) Input Signal Bandwidth -1dB (@ RIN = 33 ) -3dB (@ RIN = 33 ) REFERENCE INPUTS Reference Resistance VRT - VRB Reference Current Reference Voltage VRT VRB VRT - VRB Self Bias Voltage VRB VRT - VRB Capacitance (VRT, VRTS, VRB, VRBS) Offset Voltage VRT VRB DIGITAL INPUTS Logic Levels Input Voltage "1" Input Voltage "0" Input Current A/D CLK CLP, CLE OE Input Capacitance A/D Clock Pulse Width (tpw1) (tpw0) DIGITAL OUTPUTS Output Current (OE = 0V) (@ +DVS = +5V) "1" "0" Output Current (OE = 0V) (@ +DVS = +3.3V) "1" "0" Output Current (@ OE = +3V) "1" "0" Capacitance -- 2.2 -- -240 -240 -40 -- 10 10 MIN. -- 4 -- 2.4 -40 -40 -- -- -- -- -- -- -- -- -- TYP. -- -- -- -- -- -- 11 -- +0.8 240 40 240 11 -- -- MAX. -2 -- -1.2 -- 40 40 pF Volts Volts A A A pF ns ns UNITS mA mA mA mA A A 260 4.1 -- 0 1.7 +0.52 1.80 -- -70 20 370 5.4 -- -- -- +0.56 1.92 -- -50 40 480 7.7 +2.7 -- -- +0.60 2.04 11 -30 60 MIN. +0.5 -- -- -- TYP. -- 15 60 100 MAX. +2.5 -- -- -- UNITS Volts pF MHz MHz
t PLH t PHL (@+DVS = +3.3V) t PLH t PHL 3-State Output Enable Time (RL = 1k , CL = 15pF) (@ +DVS = +5V) t PZH t PZL (@+DVS = +3.3V) t PZH t PZL 3-State Output Disable Time (RL = 1k , CL = 15pF) (@+DVS = +5V) t PHZ, t PLZ (@+DVS = +3.3V) t PHZ, t PLZ CLAM CIRCUIT Clamp Offset Voltage Clamp Pulse Width PERFORMANCE Resolution Sampling Rate, maximum, FS minimum, FS Aperature Delay (Tds) Integral Linearity Error Diff. Linearity Error Diff. Gain Error 11 Diff. Phase Error 11 S/N Ratio with THD (fIN = 100kHz) (fIN = 500kHz) (fIN = 1MHz) (fIN = 3MHz) (fIN = 10MHz) (fIN = 25MHz) Spurious Free Dynamic Range (fIN = 100kHz) (fIN = 500kHz) (fIN = 1MHz) (fIN = 3MHz) (fIN = 10MHz) (fIN = 25MHz) POWER REQUIREMENTS Power Supply +AVS +DVS |AGND - DGND| Power Supply Current 12 1. AIS, DIS (@ +DVS = +5V) 2. AIS DIS (@ +DVS = +3.3V) Power Dissipation ENVIRONMENTAL/PHYSICAL Operating Temp. Range, Case Storage Temperature Range Package Type Weight
5.5 5.5 4.3 4.3
9.5 8.5 11.8 7.6
12.0 12.0 16.3 16.3
ns ns ns ns
2.5 2.5 3.0 3.0
4.5 6.0 7.0 5.0
8.0 8.0 9.0 9.0
ns ns ns ns
3.5 2.5
5.5 5.5
7.5 8.0
ns ns
0 1.75
20 2.75
40 3.75
mV A
mA Volts Volts Volts Volts Volts pF mV mV
8 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- 0 0.7 0.3 3 1.5 45 44 44 43 38 32 51 46 49 46 45 45
-- -- 0.5 -- 1.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- --
Bit MHz MHz ns LSB LSB % deg dB dB dB dB dB dB dB dB dB dB dB dB
+4.75 +3.0 0 -- -- -- --
+5.0 -- -- 25 23 2 125
+5.25 +5.5 100 36 33 3 180
Volts Volts mW mA mA mA mW
-40 -55
-- +85 -- +150 32-pin, plastic QFP 0.007 ounces (0.2 grams)
C C
Footnotes:
See technical note 6 Pin 25 tied to AGND and pin 17 tied to +AVS +AVS = +4.75 to +5.25V and +DVS = 3 to +5.5V, full operating tem. range. VIL = 0V and VIH = +AVS, full operating temp. range VOH = +DVS-0.8V and VOL = +0.4V, full operating temp. range +DVS = +3 to +5.5V, full operating temp. range OE: +3 to 0V change OE: 0 to +3V change 2.75s clamp pulse width, 14.3MHz sampling, 15.75kHz clamping rate The clamp pulse width given is for NTSC. For other processing systems adjust the rate to the clamp pulse cycle (1/15.75kHz for NTSC) to equal the value for NTSC. NTSC 40IRE ramp, 14.3MHz sampling 50MHz sampling, +AVS = +5V
1 1
12
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MDA_ADC-321.B01 Page 2 of 8
ADC-321
8-Bit, 50MHz Video A/D Converter
TECHNICAL NOTES
1. The ADC-321 is a monolithic CMOS device. It should be handled carefully to prevent static charge pickup. 2. It has separate power supply terminals +AVS (pins 16, 19 and 20) and +DVS (pin 10) for the internal analog and digital circuits. It is recommended that both +AVS and +DVS be powered from a single source Other external digital circuits must be powered with a separate +DVS. A time lag between the two power supplies could induce latch up when power is turned on if separate supplies are used. The operating range of +DVS is from +3.0V to +5.5V and it allows the use of a common power supply with 3.3V digital systems. The +3.3V power for +DVS in this case should be taken or derived from the +AVS supply to avoid latch up. No power supply terminal should be left open. 3. The ADC-321 has separate grounds, the analog GND (pins 22 and 23) and digital GND (pins 28 and 31). Separate and substantial AGND and DGND ground planes are required. These grounds have to be connected to one earth point underneath the device. Digital returns should not flow through analog grounds. Connect all ground lines to the power point. 4. Bypass all power lines to GND with 0.1F ceramic chip capacitors as close to the device as possible. This is very important. 5. Even though the analog input capacitance is a low 15pF, it is recommended that high frequency input be provided via a high-speed buffer amplifier. A parasitic oscillation may be generated when a high-speed amplifier is used. A 33 ohm resistor inserted between the output of an amplifier and the analog input of the ADC-321 will improve the situation. Kick back noise from A/D CLOCK pulses will be observed at the analog input terminal, but this has no influence on the ADC321 performance. 6. Apply +2.5V to VRT (pin 18, reference top) and 0.5V to VRB (pin 24 reference bottom) to obtain an analog input range of +0.5V to +2.5V. Conversion accuracy is dependent on stable reference voltages. Provide reference inputs via amplifiers that have enough driving power to avoid noise problems. Keep to the following equations; 0V VRB VRT +2.7V, | VRT - VRB | 1.7V 24) will then be +2.48V and +0.56V respectively. Under an application where this self bias function is used, the effects of temperature changes are minimal. Voltage changes of the +5V supply have direct influence on the performance of the device. The use of external references is recommended for applications sensitive to gain error, no ac signals can be used as references for this device. 7. A voltage up to +AVS + 0.5V can be applied to each digital input even when +3.3V is powered to +DVS, but the digital output voltage never exceeds +DVS. 8. Layout A/D CLOCK pulse input (pin 12) as short as possible for minimum influence on other signals. Use of a 100 ohm series resistor is recommended to protect the device as there may be some voltage difference and turn-on-time lag on the power supplies. Analog inputs signals are sampled at the falling edge of an A/D CLOCK pulse and digital data become available at the rising edge of an A/D CLOCK pulse that is delayed by 2.5 clock cycles. The A/D CLOCK are positive pulse that have 50% duty cycle. The minimum clock pulse width is 10 nsec for both high and low levels. Keep it low level while A/D conversions are on hold. 9. Digital output is 3-state. To enable 3-state outputs connect the OUTPUT ENABLE (pin 30) to GND. To disable, connect it to +DVS. The output is recommended to be latched and buffered through output registers. The device may be damaged if a voltage higher than +DVS + 0.5V is given to digital output pins while at high impedance level. 10. The 50MHz sampling rate is guaranteed. It is not recommended to use this device at sampling rates slower than 500kHz because the droop characteristics of the internal sample and hold exceed the limit required to maintain the specified accuracy of the device. Also, burst mode sampling is not recommended. 11. The ADC-321 has a clamp function. This clamp is enabled when CLAMP ENABLE (pin 29) is tied to GND and is disabled when tied to +DVS or left open. Clamp pulse inputs (pin 15) are effective when this clamp function is enabled and signals are clamped whole, this clamp pulse is low. The clamp reference input (pin 26) is set by an external trim. The CCP terminal (pin 27) integrates the clamp control voltage across an external capacitor. Refer to Figure 4 for examples of various ways to use this clamp function. 12. The TEST 1 and 2 (pins 9 and 11) are not used. Always leave them open.
The ADC-321 has a self bias function which allows the device to work without external references. Connect VRTS (pin 17, self bias top) to +AVS and VRBS (pin 25, self bias bottom) to the analog GND to obtain an analog input range of +0.56 to +2.48V. Typical voltages at VRT (pin 18) and VRB (pin
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MDA_ADC-321.B01 Page 3 of 8
ADC-321
8-Bit, 50MHz Video A/D Converter
THEORY OF OPERATION
(See Functional Block Diagram, Figure 1, and Timing Diagrams, Figure 2) 1. The DATEL ADC-321 is a 2-step parallel A/D converter featuring a 4-bit upper comparator group and two 4-bit lower comparator groups, each with built-in sample and hold. A reference voltage equal to the voltage between (VRT - VRB)/16 is constantly applied to the 4-bit upper comparator block. A voltage corresponding to the upper data is fed through the reference supply to the lower data. VRTS and VRBS pins provde the self generation function for VRT (reference voltage top) and VRB (reference voltage bottom) voltages. 2. This converter uses an offset cancelation type comparator and operates synchronously with the external clock. It features various operating modes which are shown in the Timing Diagram (Figure 2) by the symbols S, H and C. These characters stand for Input Sampling (Auto Zero) Mode, Input Hold Mode and Comparison Mode. 3. The operation of the respective parts is as indicated in Figure 2-3. For instance, input voltage N is sampled with the falling edge of the first clock by means of the upper comparator block and the lower comparator A block. Input voltage N+1 is sampled with the falling edge of the second clock by means of the upper comparator block and lower comparator B block. The upper comparator block finalizes comparison data UD(N) with the rising edge of the second clock. The lower comparator block finalizes comparison data LD(N) with the rising edge of the third clock. UD(N) and LD(N) are combined and routed to the output as Output Data N with the rising edge of the fourth clock. Thus there is a 2.5 clock delay from the analog input sampling point to the digital data output.
Table 2: Digital Output Coding
VIN 0V +7.812mV +0.9922V +1.000V +1.500V +1.9922V
OUTPUT CODE MSB LSB 0000 0000 0111 1000 1100 1111 0000 0001 1111 0000 0000 1111
tr = 4.5ns
tr = 4.5ns 90% 3V
OE INPUT
1.3V 10% tplz tpzl 1.3V 10% tphz 90% tpzh VOH/(=DGND) 1.3V VOL VOL /(=DGND) 0V VOH
OUTPUT 1
OUTPUT 2
Figure 2-1. ADC-321 Timing Diagram
tr = 4ns
tf = 4ns 90% 3V
CLOCK 1.3V 10% 0V
DATA 0. 7 DVS OUTPUTS 0. 3 DVS tpLH tpHL
Figure 2-2. ADC-321 Timing Diagram
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MDA_ADC-321.B01 Page 4 of 8
ADC-321
8-Bit, 50MHz Video A/D Converter
Tds N ANALOG SIGNAL N+1 TPW1 TPW0 N+2 0ns typ. N+3
10ns min. 10ns min.
CLOCK 1.3V TPLH TPHL
DATA OUTPUTS
N-3
N-2
N-1
N
1
UPPER SAMPLING COMPARTOR
1
S (N)
C (N)
S (N+1)
C (N+1)
S (N+2) C (N+2)
S (N+3) C (N+3)
UPPER OUTPUT DATA
1
UD (N-1)
UD (N)
UD (N+1)
UD (N+2)
LOWER SAMPLING COMPARTOR 1
1
S (N)
H (N)
C (N)
S (N+2)
H (N+2)
C (N+2)
LOWER OUTPUT DATA 1
1
LD (N-2)
LD (N)
LOWER SAMPLING COMPARTOR 2
1
H (N-1)
C (N-1)
S (N+1)
H (N+1)
C (N+1)
S (N+3)
H (N+3)
LOWER OUTPUT DATA 2
LD (N-3)
LD (N-1)
1
LD (N+1) Internal Operation of the ADC-321
S = Sample Mode, H = Hold Mode, C = Comparate Mode
Figure 2-3. ADC-321 Timing Diagram
+5V (A) 0.1F 0.1F 0.1F 0.1F 10H 16 500 47F 0.1F 500 100 17 0.1F 18 0.1F 19 10F 20 0.1F ANALOG IN 180 500 470F 120 1k 2k 0.1F 24 +12V 47F 0.1F -12V 1k 1k 10H -12V 25 26 27 28 29 30 31 32 1 5k 23 2 33 10pF 22 3 21 6 7 15 14 13 12 11 10 0.1F +5V (D) 47F 9 8 74HC04
A/D CLOCK
47F +12V +5V (A) +12V
BIT 1 (MSB) BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 (LSB)
ADC-321
5 4
5V
500
Figure 3. Typical Connection Diagram
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MDA_ADC-321.B01 Page 5 of 8
ADC-321
8-Bit, 50MHz Video A/D Converter
CLAMP PULSE +5V (A) +5V (A) +5V (D) A/D CLOCK +5V (D) A/D CLOCK
16 15 17 18 19 ANALOG IN 20 33 21 10pF 22 23 24 25 26
14
13
12 11
10
9 8 7 6 5 4 3 2 1 10F 10pF VRT ANALOG IN 33 21 22 23 24 VRB +5V (A) 20k 17 18 19 20
16 15
14
13
12 11
10
9 8 7 6 5 4 3 2 1
27
28 29
30
31
32
25 26
27
28 29
30
31
32
0.01F
Figure 4-1. Clamp Not Used in Self Bias Mode
Figure 4-2. Clamp Used in External Reference Mode
CLAMP PULSE +5V (A) A/D CLOCK +5V (D) +5V (A) A/D CLOCK +5V (D)
16 15 17 18 19 ANALOG IN 10F 20 33 21 10pF 22 23 +5V (A) 24 25 26
14
13
12 11
10
9 8 7 6 5 4 3 2 1 10F ANALOG IN 33
16 15 17 18 19 20 21 10pF 22 23 24 25 26
14
13
12 11
10
9 8 7
Comparator
6 5 4 3 2 1 27 28 29 30 31 32
Clamp Level Data
27
28 29
30
31
32
20k 0.01F 0.01F
D/A
Figure 4-3. Clamp Used in Self Bias Mode
Figure 4-4. Digital Clamp Used in Self Bias Mode
CLAMP PULSE +5V (A) +3.3V (D) A/D CLOCK
16 15 17 18 19 ANALOG IN 20 33 21 10F 10pF 22 23 +5V (A) 20k 24 25 26
14
13
12 11
10
9 8 7 6 5 4 3 2 1
27
28 29
30
31
32
0.01F
Figure 4-5. Clamp Used in Self Bias Mode With +5V/+3.3V Dual Power Supply
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MDA_ADC-321.B01 Page 6 of 8
ADC-321
8-Bit, 50MHz Video A/D Converter
Ambient Temperature vs. Sampling Delay
0
Sampling Delay (ns) Output Level (dB)
Analog Input Bandwidth
Analog Input Frequency vs. S/N + THD, Effective Bit
FS = 50MHz AVS = DVS = 5V VIN = 2Vp-p TA = 25C
1 0 -1
Effective Bit (dB)
FS = 50MHz AVS = DVS = 5V
-2 -3
FS = 50MHz Sine wave 1Vp-p input AVS = DVS +5V TA = 25C
7 6 5
SNR (dB)
-1
8
50 40 30
-20
0 +25 +50 +75 Ambient Temperature (C)
0.1
0.1 10 100 Analog Input Frequency (MHz)
1 0.1 0.01 10 Analog Input Frequency (MHz)
Analog Input Frequency vs. FSDR
60
Output Data Delay (ns)
Ambient Temperature vs. Output Data Delay
Output Data Delay (ns)
Ambient Temperature vs. Output Data Delay
12 10 8 6 -20 tplh
12 10 8 6 -20
FSDR (dB)
50 40 30 FS = 50MHz AVS = DVS = 5V VIN = 2Vp-p TA = 25C
tplh tphl FS = 50MHz AVS = DVS +5V CL = 15pF
tphl
FS = 50MHz AVS = DVS +5V CL = 15pF
0.1 1 0.01 10 Analog Input Frequency (MHz)
0 +25 +50 +75 Ambient Temperature (C)
0 +25 +50 +75 Ambient Temperature (C)
Load Capacitance vs. Output Data Delay
Output Data Delay (ns) Output Data Delay (ns)
Load Capacitance vs. Output Data Delay
Output Data Delay (ns)
Ambient Temperature vs. Output Data Delay
12 tplh 10 8 tphl 6 3 3.5 4.5 5 5.5 Ambient Temperature (C) FS = 10MHz +AVS = +5V TA = 25C
12 10 tplh 8 tphl 6 -20 FS = 50MHz AVS = DVS +5V CL = 15pF
14 12 10 8 6 0 5 tphl tplh FS = 10MHz AVS = +5V DVS = +3.3V TA = 25C
0 +25 +50 +75 Load Capacitance (pF)
10
15
20
25
Load Capacitance (pF)
Ambient Temperature vs. Supply Current
Supply Current (mA) Supply Current (mA)
Supply Voltage vs. Supply Current
Supply Current (mA)
Sampling Rate vs. Supply Current
26 25 24
FS = 50MHz AVS = DVS = +5V
27 25 23 FS = 50MHz AVS = DVS TA = 25C
25 20 AVS = DVS = +5V 15
-20
0 +25 +50 +75 Ambient Temperature (C)
4.75
5 Supply Voltage (V)
5.25
10
20 30 40 50 Sampling Frequency (MHz)
Input Frequency vs. Supply Current
Max. Sampling Rate (MHz) Supply Current (mA)
Ambient Temperature vs. Max. Sampling Rate
Sampling Rate (MHz)
Supply Voltage vs. Sampling Rate
35 30
FS = 50MHz Sine wave 1.9Vp-p AVS = DVS = +5V TA = 25C
70 65
FS = 50MHz fin = 1kHz, triangular wave input AVS = DVS +5V
67 65 AVS = DVS 63
25
60
0.01
0.1
1
10
25
-20
0
25
50
75
4.75
Input Frequency (MHz)
Ambient Temperature (C)
5 Supply Voltage (V)
5.25
Figure 5: Typical Performance Curves
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MDA_ADC-321.B01 Page 7 of 8
ADC-321
8-Bit, 50MHz Video A/D Converter
DIGITAL OUTPUT +DVS
+AVS
ANALOG INPUT
REFERENCE INPUT
+AVS
VRTS 1 to 8 21 V RT Rref RB
V RB 24 25 V RBS
DGND CLAMP REFERENCE VOLTAGE INPUT (VREF)
+AVS
AGND
AGND
A/D CLOCK
+AVS
CLAMP CONTROL VOLTAGE (CCP)
+AVS
OUTPUT ENABLE (OE)
+AVS
CLAMP PULSE INPUT (CLP) CLAMP ENABLE (CLE)
+AVS
12
28
27
30
15 29
AGND
AGND
AGND
AGND
AGND
Figure 6: Equivalent Circuits
0.35 0.008 (9.0 0.2) 0.280 0.008 (7.1 0.2) 24 17
MECHANNICAL DIMENSIONS INCHES (mm)
25
16
32 1 0.03 (0.8) 8
9
0.012 0.005 (0.03 -0.1, +0.15)
0.02 (0.5)
0.315 (8.0)
0.039 0.010 (1.5 0.35)
0.006 0.006 (0.15 0.15)
0 to 10 0.006 0.003 (0.152 0.075)
ORDERING INFORMATION
ADC-321 8-bit, 50MHz A/D converter
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Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000
Murata Power Solutions, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 U.S.A. Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356
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01/05/09
Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. (c) 2008 Murata Power Solutions, Inc.
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